Issue link: https://resources.pcb.cadence.com/i/1533024
Knowing the requirements is part of the effort. Depending on which of the four generations of PCIe we're using, the operating frequency can be 1.25 GHz, 2.5 GHz, 4 GHz, or 8 GHz with data rates at double those frequencies. Yet, all versions have the same amount of phase tolerance. First, you have to route the signals. Then you can see what you have and react accordingly. When there are differential pairs, I start out by solving for intra-pair skew (phase matching). When both the P and the N length are equal, you get more margin with the inter-pair tolerance. Any length variations between P and N eat into the available tolerance of the pair to pair length matching. While it's not a firm requirement for PCIe, there are other buses where multiple lanes need to match up in length. I try to overachieve on length matching. It's not that hard when you have a meter telling you exactly how much the traces have to meander in real time in order to meet a certain length. The Computer Says My Trace Is Too Long and Too short. Now What? That said, it can be tricky to interpret what the meter is trying to tell you. The clock can simultaneously be too long and too short while it might actually be the proper length. What that is telling you is that a member or members of the group are too short to match the clock in its current length while others are too long. If you analyze the match group, the actual lengths are shown in the constraint manager so you can easily find the longest line and work to shorten it. That effort helps the shorter ones get there with minimum jogs. When a bus is routed but not tuned, it helps to survey (analyze) the actual results before starting the meander process. Highlighting the longest trace(s) one color and the shortest another helps plan the timing resolution. Once a net is length matched to within spec, it could be given another color so you know not to slide that one around. When everything is resolved, the "fixed" property will lock the group into place so it isn't accidentally edited. Figure 2. Much like physical and spacing constraints, the Name column is a place for the Right Mouse Click to open up options. Here we're creating a new Electrical Constraint Set (ECS) using the 50_OHM ECS as a template. The general values are set in these upper pages while the nets below are broken out for selection to follow the rules from above. 3 www.cadence.com Controlling Trace Length for Digital Circuits Using OrCAD X and Allegro X Tools