Controlling Air Gaps Using OrCAD X and Allegro X
The general rule for routing is that shorter is better. Placement remains in flux as the fan-out and routing goes along. Printed
circuit boards of moderate to high complexity will feature groups of traces that are related to one another; generally in the
digital realm. These are known as busses or match groups where all of the members are of the same or similar lengths. A good
bus will feature net names that indicate the nature of the circuit.
Regardless of its exact name, one member of the group is designated as the target for the rest of the group members to guide
their length. The first step is identifying the members and their leader - if one connection is singled out as such. The OrCAD X
schematic tool has the same constraint manager as the layout tools so it's possible for the schematic to carry that data over
to the board layout.
We can expect impedance and targets in ohms while it's up to us to find a way to carry that information to the board as
stack-up geometry, line widths and air gaps. The timing budget may be a little more nebulous. The length matching infor-
mation is often part of a stand-alone spec for a type of circuit, be that DDR, EMMC, SPI, or what have you. You'll want this
information ahead of the placement process as these factors will prioritize some components over others.
We look for labels and notation on the schematic to help define the groups to be matched. There's always a tolerance to the
lengths. Sometimes, the tolerance is vanishingly small. Other times, it's rather generous. Even so, a lot of people will ask for a
better outcome than simply meeting the requirements. It may seem to be over-engineered but to truly match the line lengths
will leave enough margin to add a crucial via without derailing the timing budget.
Figure 1. Intra-Pair Skew is set to a maximum of 5 mils for PCIe busses. There is no spec for Intra-Pair Skew although the maximum length of
the traces on a board is somewhere between 12 and 15 inches according to app notes I've found regarding different generations of the spec.
Image Credit Texas Instruments
2 www.cadence.com
Controlling Trace Length for Digital Circuits Using OrCAD X and Allegro X Tools
