Issue link: https://resources.pcb.cadence.com/i/1532919
7. Expand the PRIMARY Cell, then to the right of the Conductor Cell, choose the above constraint set and apply it (DFFACS1). Now your pads and vias will throw a design rule error if they have any less than 5 mils (0.127 mm) of Annular ring available. Reason: Ensures reliable connections between layers and prevents manufacturing defects like breakouts. Impact: Affects manufacturability, reliability, and overall PCB performance. Pads may rip up. The board may result in incom- plete connections and a non-functional mess of circuitry. Drill to Copper Spacing Top view of a pad with drill hole edge to copper trace edge spacings 28 www.cadence.com OrCAD X Constraint Management Guide