Issue link: https://resources.pcb.cadence.com/i/1480208
APPLICATION NOTE 19 DC COMPONENT = 1.588979E-02 HARMONIC FREQUENCY FOURIER NORMALIZED PHASE NORMALIZED NO (HZ) COMPONENT COMPONENT (DEG) PHASE (DEG) 1 5.000E+01 5.007E+00 1.000E+00 -1.542E+02 0.000E+00 2 1.000E+02 3.474E-02 6.939E-03 1.372E+01 3.222E+02 3 1.500E+02 4.239E+00 8.466E-01 7.852E+01 5.412E+02 4 2.000E+02 4.262E-02 8.513E-03 -6.951E+01 5.474E+02 5 2.500E+02 3.000E+00 5.991E-01 -4.427E+01 7.268E+02 6 3.000E+02 5.177E-02 1.034E-02 -1.602E+02 7.651E+02 7 3.500E+02 1.789E+00 3.573E-01 -1.552E+02 9.243E+02 8 4.000E+02 5.893E-02 1.177E-02 1.062E+02 1.340E+03 9 4.500E+02 1.156E+00 2.308E-01 1.152E+02 1.503E+03 10 5.000E+02 6.495E-02 1.297E-02 1.311E+01 1.555E+03 TOTAL HARMONIC DISTORTION = 1.121256E+02 PERCENT If you observe these results carefully, you will find that contributions of the even harmonics (2nd, 4th, and so on.) are significantly less compared to the odd harmonics (3rd, 5th, and so on.). This is as expected because current waveform exhibits half wave symmetry. You can also view the Fourier spectrum of any waveform loaded in probe. Other commonly used VRM specification Similar approach can be used to perform the simulation for various other important VRM specifications, such as: Startup Delay Startup Rise Time Hold up Time Dips & Interruptions o Against the EN61000-4-11 standards Harmonic Currents o Against the EN61000-3-2, EN61000-3-3 standard PCB layout The design of a switching power converter is only as good as its layout. This necessitates very close co- ordination between the circuit designer (simulation expert) and the layout designer throughout the design and prototype phase. Once various design parameters of VRM have been verified, design can be taken to the layout stage. One of the key challenges in Switch mode power supply design implemented on boards is having proper trace width and trace clearances for various connection handling high voltage and high current. Simulation results can be leveraged to decide proper trace width and clearances as per actual current and voltage through them. This can save prototype testing phase, can help cut down both time to market, and the cost incurred in prototypes. In this design, trace width and trace clearance have been assigned based on simulation results.