Issue link: https://resources.pcb.cadence.com/i/1480200
APPLICATION NOTE 6 A Nonlinear Capacitor Model for Use in PSpice The charge and current formulas for a linear capacitor are: Q = C * V (1a) I = C * dV(t)/dt (1b) For a nonlinear (voltage-dependent) time-independent capacitor these formulae become: Q = ò C(V) * dV (2a) I = C(V) * dV/dt (2b) This applies to cases where the capacitance has been measured at different bias voltages. Some would argue that for a nonlinear capacitor, Q = C(V) * V (3a) where V is a function of time. Therefore, I = dQ/dt = C(V(t)) * dV(t)/dt + dC(V(t))/dt * V(t) (3b) This is not correct. The flaw in this argument is equation (3a). Although (1a) holds true for linear capacitors, the generalized definition of charge is (2a). Capacitance is the partial derivative of Q with respect to V; which means I = dQ/dt = ¶Q/ ¶V * dV/dt = C(V) * dV/dt (4) Given this relationship between the current through a nonlinear capacitance and the voltage applied to it, analog behavioral modeling can be used to model any nonlinear capacitor whose capacitance, C(V), is a function of the voltage applied to it. The Model The nonlinear capacitor is modeled by a subcircuit in which the capacitor is replaced by a controlled current source, Gout, whose current is defined by (2b). In the subcircuit, the time derivative, dV(t)/dt, is measured by applying a copy of the voltage across Gout to a known capacitance, Cref, and monitoring its current. The C(V) function in the subcircuit is arbitrary. The value of the nonlinear capacitor model in this example has a second order polynomial dependence on its voltage. This is equivalent to the standard PSpice capacitor model, whose linear and quadratic coefficients, VC1 and VC2, can be defined in a .MODEL statement. * Polynomial Nonlinear Capacitor Model .subckt polycap 1 2 params: C0=1u C1=0 C2=0 Ecopy 3 6 1 2 1.0 ; copy V(t) Vsense 0 6 0V ; Ammeter Cref 3 0 1.0E-6 ; to get 1E-6*dv/dt ; *1E-6 to avoid ridiculous currents Gout 1 2 VALUE = + {(C0 + C1*V(1,2) + C2*V(1,2)*V(1,2)) * I(Vsense)*1E6 } * ------------------------------------ ------------- * C(V) dV(t)/d .ends In Figure 7, the two circuit simulate the following two voltage controlled capacitors: A capacitor model with C0=1, C1=2,C2=0 is used in the circuit on left-side in Figure 7, making capacitance linearly proportional and twice the value of input voltage. A capacitor model with C0=1, C1=2,C2=0 is used in the circuit on right-side in Figure 7, making capacitance value Co + C*V + C*V*V. Simulation results of both the circuits are shown below in Figure 8. The top plot shows the input voltage waveforms and bottom plots capacitance values by plotting I*dV/dT of capacitor.