APPLICATION NOTE
3
Figure 4: Error Detect Logic
Implementation
The frequency-comparator circuit is designed in OrCAD Capture using hierarchical blocks for the initializer (INIT
block), cycledetectors (PICD blocks), state-decoder (SDL block), and errordetector (EDL block). The design has
two alternative implementations: a gate-level implementation using off-theshelf 74xx parts (see Figure 5), and a
functionally equivalent implementation using a mixture of 74xx parts and a commonly available Programmable
Array Logic (PAL) device, PAL20RP4B (see Figure 6). Both implementations use the digital stimulus include
file,Freq_comparator.stm, providing definitions for the INIT, RUN, MODE, REFH, REFH, FTEST, and SYSCLK
input signals. The design alternatives are implemented as two views of the SDL block, with the DEFAULT view
being the gate-level implementation, and the PAL-IMPL view being the PAL implementation. For the PAL-IMPL
view, the data required to program the PAL20RP4B device is supplied in a JEDEC file, FRQCHK.JED, generated
using OrCAD/PLD.
