APPLICATION NOTE
1
Introduction
This application note illustrates how a hierarchical all-digital design with two implementation views, can be defined
in OrCAD Capture, and subsequently simulated in PSpice. The example circuit is a basic frequency-comparator
(see Figure 1). All parts used in the schematic are provided in the standard Symbol and Model Libraries. One
implementation is chosen for PSpice simulation to demonstrate the circuit's behavior.
Figure 1: Top-level schematic for the frequency-comparator circuit
The frequency-comparator circuit accepts two reference frequency inputs, and a test frequency input which is
compared to the references. After initialization and start-up, the circuit produces fast, slow, OK, and error
indications. Operation is continuous as long as both of the reference signals are applied. Initialization is
accomplished by applying a low pulse to the INIT input, having a minimum width of 40 nsec. At least 40 nsec after
the negative-going edge of the INIT input, circuit operation commences upon applying a negative-going edge to
the RUN input. Outputs of the circuit–SLOW, FAST, OK, and ERROR–are pulses indicating the result of
comparing the test frequency signal, FTEST, to the low and high frequency reference signals, REFL and REFH,
respectively. The ERROR pulse is generated if more than 7 complete periods of the REFL signal are observed
with no activity on the FTEST input during that time.
