Issue link: https://resources.pcb.cadence.com/i/1436019
The Company Cavium develops highly integrated semiconductor processors for intelligent networking, communications, storage, video, and security applications. Based in San Jose, California, the company also has design teams in Massachusetts, India, Taiwan, and China. Bill Munroe is a principal PCB designer at Cavium, where he and a colleague on the Post-Silicon Validation team design evaluation boards used to confirm the correct operation and electrical characteristics of the company's network processors. The pair works on multi-layer boards for high- speed SerDes designs, typically with layer counts similar to those found in system server boards, averaging 12,000 unrouted connections and 3,000 nets. Key Challenges Board routing had been a time-consuming, manual process— especially as chips increasingly use standards-based high- speed interfaces (such as DDRx, PCI Express ® , etc.), have increasingly sensitive signals, and have more complex electrical and layout implementation constraints. Munroe and his colleague were using Allegro PCB Router auto-router for miscellaneous logic (and continue to do so today). But they were routing critical high-speed signals by hand, which typically took 8 to 12 weeks to lay out from start to finish, without using additional human resources. Meantime, schedule pressures were increasing as the volume of chips requiring evaluation boards grew. "As we're doing our board design, we're doing our chip pin-outs. Not only are we routing our boards once, we're selling our processors to customers who will be routing these boards over and over again," explained Munroe. "We want to give our customers the best processor pin-out we can, make sure that our chip works very well, and ensure that our customers have ease of use as far as routability." It's critical for the PCB design team to have their boards ready when the chip comes back from the fab. "As we grow the number of network processors we offer, the number of designs that we do increases. So we needed to look at where we could save time," said Munroe. The Solution and Results The Cavium team didn't have to look far for a solution, as Munroe explained: "We're a Cadence shop." The team imple- mented the Allegro TimingVision environment, available within the Allegro PCB Designer constraint-driven PCB design environment (High-Speed Option). The team also uses Allegro Constraint Manager for design constraint management. 4X Faster Timing Closure on High-Speed Interfaces with Allegro TimingVision Environment Cavium and Cadence Challenges • Address increasing schedule pressures for complex, high-speed evaluation boards • Accelerate timing closure process while maintaining high quality of boards • Take on more projects with current staffing level Cadence Solution • Allegro ® TimingVision ™ environment • Allegro PCB Designer • Allegro PCB Router (previously known as SPECCTRA ® ) Lessons Learned • Route DDR4 signals spaced at 5X the line width for better noise /coupling immunity • Ensure that differential pairs (static and dynamic phases) are all matched before trying to match lengths for all signals in a byte lane • Use application modes within Allegro PCB Designer to further increase tuning efficiency • Take advantage of user-redefinable, application- mode-sensitive "funckeys" to further shorten overall tuning proces Results • 4X faster timing closure, without compromise on quality • Ability to take on increased volume of PCB designs with existing resources • Faster "what-if" analysis with fewer layers for boards for routing DDRx interfaces