Issue link: https://resources.pcb.cadence.com/i/1436019
www.cadence.com 2 Annapurna mountain The Allegro TimingVision environment has transformed Cavium's PCB design process. With their manual process, Munroe and his colleague had to switch back and forth between their design canvas and Allegro Constraint Manager, and timing closure was completed iteratively. Feedback was delivered on a matched group level, so all signals had to meet timing before the group could go "green." They had to manually calculate all interdependencies and margins between groups. Now, Munroe and his colleague have real-time, color-coded visual feedback on timing and phase information right on their design canvas. The technology's embedded timing engine analyzes signal interdependencies to develop smart delay and phase targets. "With Allegro TimingVision, everything is right there in front of you—this simple fact allows the routing process to be sped up dramatically, from the manual routing efforts we have seen that can take up to four weeks, down to four days," noted Munroe. "The color overlays on the routes guide us to constraint resolution, so we don't have to rely on parsing information in Allegro Constraint Manager. We can perform faster "what-if" analysis with fewer layers for our boards for routing study designs using DDRx interfaces." Using the Allegro technology, Munroe routed four DDR3 channels on one evaluation board in less than four days. Done manually, this would have taken four weeks. In another case, a customer was unsure whether the team could complete routing on four signal layers on a two-channel DDR design within the targeted timeframe. "As an example of what is possible with this tool, we did it in two days. Manually, this would have taken two weeks," said Munroe. Figure 1: Initial bundling and planning stages for two-channel customer-defined placement. Allegro tools were used to generate and order the interconnect bits to be routed within each bundle. Figure 2: Cadence's auto-interactive routing tools helped to successfully route this design with four internal signal layers. The Cavium PCB designers also take advantage of some auto- interactive technologies while using the Allegro TimingVision environment. Auto-interactive Delay Tuning (AiDT) technology adjusts timing of the signals to meet constraints. "As an example, I can select one 12-signal DDR data byte, and use match group selection mode to tell me what the target length is. I can then adjust the match target length with AiDT, and add lengths as needed to get the line to meet the target," Munroe explained. The designers use Auto-interactive Breakout Technology (AiBT) with Auto-interactive Trunk Routing (AiTR) to determine whether pin-outs as proposed by the silicon package group will require more layers to break out and route to the network processor. These tools help to quickly propose new pin-outs—an advantage particularly for complex interfaces such as DDRx. With the Allegro technologies, Munroe and his colleague can handle a larger volume of board designs—without having to spend all night in the office. "Designers don't need to sit here hour after hour after hour and bang their head to get something done. With the high-quality Allegro tools available, we can deliver high-quality work with greater efficiency than in the past," he said. Lessons Learned As Cavium has enhanced its PCB design process, Munroe notes that when routing DDR4 designs, it's best to route signals spaced at 5X the line width for better noise/coupling immunity. "I get a true serpentine and all of the lengths I'm looking for. My rule of thumb: if the space is available, use it," he said.