Issue link: https://resources.pcb.cadence.com/i/1310899
Cadence ® Sigrity ™ SPEED2000 ™ technology provides for direct layout-based, time-domain simulations of an entire board design or for a specific IC package together with the PCB. These simulations can include various SPICE/S-parameter interconnect models and component models commonly used in signal integrity (SI)/power integrity (PI) simulations. The Sigrity SPEED2000 engine combines circuit solver and transmission line solver with a fast electromagnetic (EM) field solver to capture dynamic interactions between signal, power, and ground on signals and planes in one time-domain simulation. Using the tool, you can perform a broad range of workflows for various levels of SI and PI analysis as well as electromagnetic interference (EMI) and electro-static discharge (ESD) studies in a single environment. Sigrity SPEED2000 Layout-based, time-domain signal integrity/power integrity/electromagnetic interference simulations Sigrity SPEED2000 ERC Electrical rule checking (ERC) is a fast and easy way to scan a full board for first-order electrical design problems without the requirement for IBIS models. These checks fill in the gap between a geometry-based design rules check (DRC) and a simulation- based signoff simulation task performed with IBIS models. Basic ERC Trace impedance, coupling, and return path discontinuity checks provide a micro view of layout trace properties, which are useful for design and debug. Using this technology, you can quickly screen the board layout to get: • A high-level summary of impedance and coupling results by net, including number of vias, number of return path discontinuities, and number of trace sections over voids, trace lengths, and trace delays • Detailed/interactive checks by trace segment, including collapsed and expended plots, layout overlay, and plots to layout over cross-probing • Both single-ended and differential impedance and coupling Figure 1: An example of trace coupling check results