OrCAD datasheets

www.cadence.com 2 Sigrity SPEED2000 • Violation reports, based on your defined thresholds, will be formatted in tables and can be highlighted in layout Trace check results are bundled by net groups, making the comparison easy and meaningful. Set up of net groups is easy and automated. Based on the trace check results, you can easily see the impedance/ coupling distribution to identify the viola- tions in the plots, and use cross-probing to locate the violations in the layout. Reports are available in HTML. Simulation-based ERC Simulation-based rule checking provides a more detailed view of overall SI perfor- mance, which is useful for additional screening and design reviews before moving on to detailed power-aware SI analysis for signoff. Simulation-based electrical rule checks rely on time-domain simulations that consider crosstalk and non-ideal power and ground supplies, without having to assign IBIS models. Save time when checking on a large number of nets with an easy-to-use workflow combined with a high level of automation and parallel computing. Generated results include: • TX /RX waveforms and worst-case NEXT/FEXT waveforms • SI performance metrics based on signal magnitudes, inter-symbol interference (ISI) and crosstalk at receivers • Top 10 crosstalk aggressors • Extensive checking reports Simulation-based electrical rule checks can be used in the following cases: • To screen boards and identify worst cases for further analysis • To investigate SI impact of design rule violations and tradeoffs • To compare against a known good design or reference design Power-aware ERC When run with a non-ideal PDN, simulation-based rule checking can be expanded to simulate the impact of power noise and the coupling to signals. These expanded checks include: • Plane ringing that couples to reflections from signal impedance discontinuities • Plane ringing that couples to signals generating new crosstalk • Plane ringing that increases crosstalk between coupled signals • Delay impacted by power or ground plane noise • Impact of signal vias coupling to power and/or ground planes causing ringing that impacts reflection and crosstalk results DDR Simulation with Sigrity SPEED2000 and SystemSI Tools Due to complexities in setting up DDR simulations as well as interpreting the post-simulation results, Cadence recom- mends driving DDR simulations from the Sigrity SystemSI tool. The Sigrity SPEED2000 tool plays an important role in moving from initial reflection simulations to signoff-level power-aware simulations that include the impact of simultaneous switching noise. Initial simulations can be driven from the Sigrity SystemSI tool using extracted SPICE models created by Sigrity SPEED2000 workflows. For final signoff, the same user interface in the Sigrity SystemSI tool can be used to drive the Sigrity SPEED2000 FDTD-direct workflow where the interactions between signal, power, and ground are all included. Figure 2: An example of SI metric check results FDTD-Direct Simulation Sigrity SPEED2000 Select signals and set up simulation parameters in the physical layout Sent back to Sigrity SystemSI Set up controller model and memory models FDTD simulator called in background Power-aware simulation results displayed in Sigrity SystemSI Figure 3: Power-aware DDR flow using FDTD-direct simulation

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