OrCAD datasheets

www.cadence.com 2 Allegro Design Authoring schematics. Schematic Editor also allows you to place multiple discrete components quickly. For example, to place 512 resis- tors that tie into a 512 bit bus, you need only place one resistor on the bus and specify that 512 such components need to be placed, and Schematic Editor will connect 512 bits to 512, greatly reduc- ing the number of graphical components needing to be placed and displayed within a design. The Allegro Design Authoring point-to- point wire router makes it easy to connect ports on two different symbols, saving time to create the schematics. Similarly, automatic insertion of a two-pin com- ponent within an existing net generates associated input and output pins auto- matically while adhering to the associ- ated net names, shortening time to create basic schematics. Whether you're using a flat design with a few hundred sheets or a hierarchical design with multiple levels of hierarchy, Global Navigate allows you to navigate to any net or part in your design with a few mouse clicks. The dock-able Global Find and Replace window allows you to find and replace parts or properties across the design. These can be highlighted directly from Allegro PCB Editor or Allegro PCB SI. Customizable Rules Checking Allegro Design Authoring eliminates mul- tiple design iterations with Rules Checker, a truly comprehensive verification facil- ity. It allows you to perform electrical and design rule checks to verify drafting standards and correct property names, syntax, and values. Rules Checker also includes rules to support downstream processing, fan-in and fan-out errors, load errors, power requirements, and cost requirements. Rules Checker checks the alignment between logical and physical designs. In addition, it lets you define cus- tom rules to ensure conformity to design requirements specific to your company or your projects. Rules Checker can be used for schematics, symbols, and the physi- cal netlists. It has a rule development and debugging environment for defining rules and can run in batch mode, facilitating deployment in an enterprise environment. Design Reuse with Module Design Most designs start from other designs or reuse significant parts of existing designs. Allegro Design Authoring gives you mul- tiple choices for reuse, so you can select the most effective approach for their design. Sheets from old designs, blocks, or entire designs can be reused, which reduces rework and errors. You can copy single or multiple sheets from one design to another using the Import Sheet UI, or just copy/paste special circuitry among different designs. You can reuse electrical constraints as part of a block or by using electrical constraint sets (ECSets). The technology further allows you to create "reuse" blocks and place them in a library for use in other designs, just as with com- ponents. The connectivity, constraints, and layout from each block can also be reused. The same block can be used multiple times in the same design without renaming or copying. FPGA Design-In Allegro Design Authoring provides a com- prehensive FPGA design-in solution. The Build Physical Wizard allows you to import Xilinx, Actel, and Altera FPGAs into your Allegro Design Authoring schematic and automatically creates the files required to drive Allegro PCB Editor, Allegro Design Authoring, and the digital simulation flow. Allegro Design Authoring also intelli- gently manages the interface to the FPGA so that the board schematic changes when the FPGA pin assignments change, but the design does not change logically. FPGA-PCB Co-Design Integrated with Allegro Design Authoring, Allegro FPGA System Planner provides a complete, scalable solution for FPGA- PCB co-design that allows you to cre- ate an optimum correct-by-construction pin assignment. FPGA pin assignment is synthesized automatically based on user-specified, interface-based connectiv- ity (design intent), as well as FPGA pin assignment rules (FPGA rules), and actual placement of FPGAs on PCB (relative placement). With automatic pin assign- ment synthesis, you avoid manual error- prone processes while shortening the time to create initial pin assignment that accounts for FPGA placement on the PCB (placement-aware pin assignment syn- thesis). This unique placement-aware pin assignment approach eliminates unnec- essary physical design iterations that are inherent in manual approaches. FPGA System Planner reads Allegro Design Authoring symbols and creates Allegro Design Authoring schematics. It also integrates with Allegro PCB Editor, from which it uses existing footprint libraries via a floorplan view. Should placement change during layout, pin optimiza- tion using FPGA System Planner can be accessed directly from Allegro PCB Editor. Design Variants By leveraging the design variants capabil- ity in Allegro Design Authoring, you can conserve even more time and effort at the structural level. The design variants capa- bility eliminates having to create slightly different versions of the same basic design—for example, offering graduated performance levels to different market segments, or addressing varying regional requirements. It enables you to derive variants of a single base design by assign- ing alternate sets of attributes to the components, wires, or other elements of the design. An engineering change order (ECO) applied to the base design auto- matically propagates to all its variants. Bill of Materials Generation Allegro Design Authoring gives you fine- tuned control over bill of materials (BOM) creation, ensuring parts lists that meet your needs precisely and contain every- thing necessary for manufacturing. You can generate a BOM for a base design or any of its variants, list non-electrical parts in a callout file, and have Allegro Design Authoring merge them in the BOM with the electrical parts from the schematic. You can associate electrical and non- electrical parts in the schematic—for example, a heatsink with an IC—and have that association shown in the BOM. You can output the BOM in ASCII text, spreadsheet, or HTML format as needed to optimize transmission to manufacturing and other recipients.

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