Issue link: https://resources.pcb.cadence.com/i/1310872
The Cadence ® Allegro ® FPGA System Planner addresses the challenges that engineers encounter when designing one or more large-pin-count FPGAs on the PCB board—which includes creating the initial pin assignment, integrating with the schematic, and ensuring that the device is routable on the board. It delivers a complete, scalable technology for FPGA-PCB co-design that automates creation of optimum "device-rules-accurate" pin assignment. By replacing manual, error-prone processes with automatic pin assignment synthesis, this unique placement-aware solution eliminates physical design iterations while speeding optimum pin assignment. Allegro FPGA System Planner FPGA-PCB co-design with automatic rules-driven pin assignment Designing Large-Pin-Count FPGAs on PCBs Integrating today's FPGAs—with their many different types of assignment rules and user-configurable pins— on PCBs is time consuming and extends design cycles. Often the pin assignment for these FPGAs is performed manually at a pin-by- pin level in an environment that is unaware of the placement of critical PCB components that are connected to FPGAs. Without understanding the impact to PCB routing, FPGA-based design projects are forced to choose between two poor options: live with suboptimal pin assignment, which can increase the number of layers on a PCB design; or deal with several unnecessary iterations at the tail end of the design cycle. Even with several iterations, this manual and error-prone approach can result in unnecessary PCB design re-spins. With the added time required to generate pin assignments for FPGAs using manual approaches, users are unable to do tradeoffs between the different FPGA devices available and the cost of devices used in an FPGA sub-system. This is because performing the tradeoffs would mean that users would have to do two projects in parallel with no design reuse of any kind between the two. Allegro FPGA System Planner The Allegro FPGA System Planner provides a complete, scalable solution for FPGA-PCB co-design that allows users to create an optimum correct- by-construction pin assignment. FPGA pin assignment is synthe- sized automatically based on user- specified, interface-based connectivity (design intent), as well as FPGA pin assignment rules (FPGA rules), and actual placement of FPGAs on PCB (relative placement). With automatic pin assignment synthesis, users avoid manual error-prone processes while shortening the time to create initial pin assignment that accounts for FPGA placement on the PCB (placement-aware pin assignment synthesis). This unique placement- aware pin-assignment approach elimi- nates unnecessary physical design iterations that are inherent in manual approaches. With a way to quickly synthesize optimum pin assignment using user- specified design intent at a high level, Cadence FPGA System Planner technologies are available as: • Allegro 2 FPGA System Planner Option • Allegro 4 FPGA System Planner Option • Allegro ASIC Prototyping Option • OrCAD FPGA System Planner