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5
Allegro FPGA System Planner
Feature DEMO
Allegro 2 FPGA
System Planner
Option
Allegro 4 FPGA
System Planner
Option
Allegro ASIC
Prototyping
Option
Max number of FPGAs in a design No limit 2 4 No limit
Max number of pins with multiple FPGAs No limit 2,000 4,000 No limit
Define connectivity at interface level
• • • •
Automatic pin assignment based on rules,
connectivity
• • • •
Define JTAG chain manually
• • • •
Define PROM chain manually
• • • •
Forward annotation of component
placement
• • •
Generate symbols and schematics
• • •
Export to PDF
• • •
Import constraints from Altera,
Xilinx, and Actel
• • •
Generate PlanAhead and Quartus scripts
• • •
Generate OrCAD Capture (symbols,
schematics)
• • •
Customization through TCL
• • •
Group signals from one bank to another
• • •
Define terminations in FSP
• • • •
Power mapping
• • • •
HDL port mapping
• • •
Use terminators from standard library
• • •
Update placement from board file
• • •
Create part from Allegro Design Authoring
symbol
• • •
Generate Allegro Design Authoring
(symbols, schematics)
• • •
Manual pin swapping in Allegro
PCB Editor
• • •
Auto generate JTAG chain
• • •
Auto generate PROM chain
• • •
Create Virtual interface
• • •
Create Virtual interface from other sources
• • •
Route Planning – Reoptimize a group of pins
to reduce rat crossovers in Allegro PCB Editor
(Using FPGA System Planner as an engine)
• •
