OrCAD datasheets

www.cadence.com 7 Allegro PCB Design Solution Allegro PCB Designer Base Plus Options Features Feature Allegro PCB Designer Allegro Design Authoring • Allegro Design Entry CIS • Constraint Manager: Physical, spacing, and samenet rules • Constraint Manager: Properties and DRCs • Constraint Manager: Differential pair rules • Constraint Manager: Region rules • Floorplanning, placement, placement replication • DFA, DFF, DFT • Dynamic feedback on DFA compliance during placement • IDF3.0, DXF in/out • EDMD schema-based ECAD-MCAD co-design • Native 3D viewer • Hierarchical interconnect flow planning • Length-based rules for high-speed signals • Constraint-driven flow for length-based high-speed signals • Match groups, layer sets, extended nets • T-point rules (pin to T-point) • 6-layer automatic shape-based autorouter • High-speed rules-based autorouting • Layer-specific rules-based autorouting • Design planning - plan spatial feasibility analysis and feedback Design Planning Option Design planning - generate topological plan Design Planning Option Design planning - Convert topological plan to traces (CLINES) Design Planning Option Auto-interactive Delay Tuning High-Speed Option Constraint Manager: Electrical rule set (relection, timing, crosstalk) High-Speed Option Constraint-driven flow using electrical rules High-Speed Option Electrical constraint rule set (ECSets) / topology apply High-Speed Option Formula and relationship-based (advanced) constraints High-Speed Option Backdrilling High-Speed Option Die2Die pin delay, dynamic phase control, Z-axis delay High-Speed Option Return path management for critical signals High-Speed Option Constraint Manager: HDI rule set Miniaturization Option Micro-via and associated spacing, stacking, and via-in-pad rules Miniaturization Option Constraint-driven HDI design flow Miniaturization Option Manufacturing rule support for embedding components Miniaturization Option Embedd components on inner layers Miniaturization Option HDI micro-via stack editing Miniaturization Option Dynamic shape-based filleting, line fattening, and trace filleting Miniaturization Option Hug contour routing (Flex) Miniaturization Option Support for cavities on inner layers Miniaturization Option Concurrent team design - layer-by-layer partitioning Team Design Option Concurrent team design - functional block partitioning Team Design Option Concurrent team design - team design dashboard Team Design Option Concurrent team design - soft nets Team Design Option Edit constraints in a partition Team Design Option Manage netclasses in a partition Team Design Option Parameterized RF etch elements editing Analog /RF Option Asymmetrical clearances Analog /RF Option Bi-directional interface with Keysight ADS Analog /RF Option High-Speed Constraints-Driven Autorouting High-speed routing constraints and algo- rithms handle differential pairs, net sched- uling, timing, crosstalk, layer set routing, and the special geometry requirements demanded by today's high-speed circuits. The autorouting algorithms intelligently handle routing around or through vias, and automatically conform to defined length or timing criteria. Automatic net shielding is used to reduce noise on noise- sensitive nets. Separate design rules may be applied to different regions of the design; for example, you can specify tight clearance rules in the connector area of a design and less stringent rules elsewhere. Operating System Support Allegro Platform Technology: • Sun Solaris • Linux • IBM AIX • Windows OrCAD Technology: • Windows

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