OrCAD datasheets

www.cadence.com 6 Allegro PCB Design Solution the panel specification and instructions for successful fabrication, assembly, and inspection of their designs. Design Data Transfer to Manufacturing A full suite of phototooling, bare-board fabrication, and test outputs, including Gerber 274x, NC drill, and bare-board test in a variety of formats, can be generated. More importantly, Cadence supports the industry initiative toward Gerber-less manufacturing through export and import of design data in IPC-2581 format. The IPC-2581 data is passed in a single file that creates accurate and reliable manu- facturing data for high-quality manufac- turing. Users have a choice to export a subset of the design data for protecting their IP. Import of IPC-2581 is intended for overlaying artwork data on the design for viewing purposes only. Miniaturization Option Constraint-Driven HDI Design Flow With BGA pin pitches decreasing to below 1mm, (0.8mm or lower with 0.65mm or 0.5mm pin pitches), users are forced to implement a buildup PCB technology using HDI. While miniaturization is not necessar- ily the primary objective in many market segments, the move to buildup technol- ogy is necessary for fanning out a BGA— particularly if it has three or four rows of pins on each side. The Allegro PCB Designer Miniaturization Option offers a proven constraint-driven HDI design flow with a comprehensive set of design rules for all different styles of HDI designs, from a hybrid buildup/ core combination to a complete buildup process like ALIVH. In addition, it includes automation for adding HDI to shorten the time to create designs that are correct by construction. Embedded Components Reducing end product size can be accom- plished in many different ways. One of the approaches PCB designers are taking is to embed packaged components on inner layers. The Miniaturization Option offers constraint-driven embedded compo- nent placement and routing. It supports direct- and indirect-attach techniques, and supports embedding components with dual-sided contacts, vertical components, and embedding in dielectric on a two-layer PCB. Additionally it offers the ability to create and manage cavities on layers speci- fied for embedding components. Analog/RF Option The Allegro PCB Designer Analog/RF Option offers a mixed-signal design envi- ronment, from schematic to layout with back annotation, proven to increase RF design productivity up to 50%. It allows engineers to create, integrate, and update analog/RF/microwave circuits with digi- tal/analog circuits in the Allegro PCB Design environment. With its rich layout capability and powerful interfaces with RF simulation tools, it allows engineers to start RF design from Allegro Design Authoring, Allegro PCB Designer, or Keysight Technologies Advanced Design System (ADS). Team Design Option Globally dispersed design teams are on the rise, which compounds the challenge of shortening design cycle times. Manual workarounds that address multi-user issues are time-consuming, slow, and prone to error. The Allegro PCB Designer Team Design Option provides a multi-user, concurrent design methodology for faster time to market and reduced layout time. Multiple designers working concurrently on a layout share access to a single database, regardless of team proximity. Designers can partition designs into multiple sections or areas for layout and editing by several design team members. Designs can be partitioned vertically (sections) with soft boundaries or hori- zontally (layers). As a result, each designer can see all partitioned sections and update the design view for monitoring the status and progress of other users' sections. Such partitioning can dramati- cally reduce overall design cycles and accelerate the design process. Routing Option The Allegro PCB Designer Routing Option is tightly integrated with the PCB Editor. Through the Routing Option interface, all design information and constraints are automatically passed from the PCB Editor. Once the route is completed, all route infor- mation is automatically passed back to the PCB Editor. Increased design complexity, density, and high-speed routing constraints make manual routing of PCBs difficult and time-consuming. The challenges inher- ent in complex interconnect routing are best addressed with powerful, automated technology. The robust, production- proven autorouter includes a batch rout- ing mode with extensive user-defined routing strategy control as well as built-in automatic strategy capabilities. DFM Rules-Driven Autorouting The design for manufacturing capabil- ity within the Routing Option signifi- cantly improves manufacturing yields. Manufacturing algorithms provide a spreading capability that automatically increases conductor clearances on a space-available basis. Automatic conduc- tor spreading helps improve manufactu- ability by repositioning conductors to create extra space between conductors and pins, conductors and SMD pads, and adjacent conductor segments. Users gain the flexibility to define a range of spacing values or to use the default values. Mitered corners and test points can be added throughout the routing process. The manufacturing algorithms auto- matically use the optimal setback range, starting from the largest to the smallest value. Test point insertion automatically adds testable vias or pads as test points. Testable vias can be probed on the front, back, or both sides of the PCB, support- ing both single side and clamshell testers. Designers have the flexibility to select the test point insertion methodology that conforms to their manufacturing require- ments. Test points can be "fixed" to avoid costly test fixture modifications. Test point constraints include test probe surfaces, via sizes, via grids, and minimum center-to- center distance.

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