Cadence PCB Best Practices

Rigid Flex

Issue link: https://resources.pcb.cadence.com/i/1180288

Contents of this Issue

Navigation

Page 43 of 44

Allegro/OrCAD Rigid Flex Design Creation Best Practices _______________________________________________________________________ Learn more at Cadence Online Support - https://support.cadence.com Page 44 © 2016 Cadence Design Systems, Inc. All rights reserved worldwide. 2 Inside 1 with a v al ue o f 0 .0 0 Limitations of InterLayer Checks Inter layer checks do not: Permit checking between Etch Layers, such as TOP etch to BOTTOM etch Same Layer checks (Coverlay_top to Coverlay_top) Distinguish between a Trace (Cline) or copper area (Shape). Other Classes, Subclasses, and objects that are not included in the Inter Layer checks are: Drawing format Analysis DRC Text (on any subclass) Board geometry outline Silk Screen layers Named dielectric layers The subclasses enabled for InterLayer checking are : Conductor Layers (No Text) Place Bound (TOP/EMBEDDED/BOTTOM) Pin/Via Layers Filmmask (TOP/BOTTOM) All Mask Layers (stackup defined) Soldermask(TOP/BOTTOM) Rigid Flex Subclasses Pastemask(TOP/EMBEDDED/BOTTOM) Surface Finshes Subclasses User Defined Subclasses* *User defined subclasses in excluded classes are not enabled.

Articles in this issue

Links on this page

view archives of Cadence PCB Best Practices - Rigid Flex