Cadence PCB Best Practices

Constraint Compiler User Guide

Issue link: https://resources.pcb.cadence.com/i/1180274

Contents of this Issue

Navigation

Page 13 of 25

Allegro Constraint Compiler User Guide Allegro Constraint Compiler October 2019 16 Product Version 17.4-2019 © 1999-2019 All Rights Reserved. Column Header Description Design Object Selection Selection of design object names can be done using explicit name, partial name with number range or regular expression or a combination of both. For example, ■ Number range for nets DDR_DQ<7> through DDR_DQ<16> would be DDR_DQ<{7-16]> ■ Regular expression for nets DDR_CK0_N and DDR_CK0_P would be DDR_CK0_[N,P] ■ Regular expression and number range for nets HSI_N0, HSI_P0, HSI_N1, HSI_P1 would be HSI_[N,P]{0-1}

Articles in this issue

view archives of Cadence PCB Best Practices - Constraint Compiler User Guide