XNet Creation and SI Simulation in Allegro System Capture
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Simulating Allegro System Capture Design
SI Simulation can be done either with Allegro PCB SI or Sigrity. For simulation
purposes, SI models need to be assigned to the devices.
• For Allegro PCB SI, SI models are defined with the SIGNAL_MODEL property
• For Sigrity, the SI models are defined with the ASI_MODEL property
These attributes are defined in the chips.prt or part table file.
Example for signal model defined in chips.prt file.
body
PART_NAME='74ALS192';
FAMILY='ALSTTL';
BODY_NAME='ALS192';
TECH='74ALS';
JEDEC_TYPE='SOIC16';
PHYS_DES_PREFIX='U';
CLASS='IC';
POWER_PINS='(VCC:16)';
POWER_PINS='(GND:8)';
SIGNAL_MODEL='DS90C031TM';
end_body;
In the following example net2 and net2_X together become one XNet.
The XNets created can be seen in Constraint Manager. When you hover over any of
nets, you see the XNet name.
