XNet Creation and SI Simulation in Allegro System Capture
Learn more at Cadence Online Support - http://support.cadence.com
© 2019 Cadence Design Systems, Inc. All rights reserved w orldw ide. Page 6
o The NO_XNET_CONNECTION property is found on the instance
In an Allegro System Capture design, XNets are created for discrete symbols
automatically or manually depending on the directive value set. For ICs, the pin level
property XNET_PINS is used for determining the pins whose connected nets create an
XNet.
Directive for Controlling XNet Creation
A directive called AUTO_XNETS_USING_GATES is defined in the START_CANVAS section of
the project cpm or site.cpm file. This directive:
• Is read by Allegro System Capture at the time of project creation.
• Defines the XNet creation mode
o Value of ON means automatic XNet creation mode
Set as ON in the cds.cpm file for Allegro System Capture. This means, that, by
default, if any discrete is placed, XNet gets created automatically.
o Value of OFF means manual XNet creation mode
In this case, XNets get created for components where the pins have XNET_PINS
defined. XNET_PINS can be defined in the chips.prt file or on the schematic.
DE-HDL Designs in Allegro System Capture
When you import a DE-HDL design to Allegro System Capture, all the needed
conversions are done automatically. DE-HDL designs can either be DML-enabled or
DML-independent. While importing to Allegro System Capture, they are converted to
DML-independent mode and XNet creation mode is decided by what is set for Allegro
System Capture designs. The SIGNAL_MODEL property is not removed from any of the
instances in the DE-HDL design, so that the SI simulation flow continues to work.
If you import sheets from DE-HDL, the XNet data or constraints data does not get
imported. To retain XNet and constraints data, use the Import Block feature.
