Enabling CM on Existing Schematic Design with Constraint Added in PCB Layout: RAK
Learn more at Cadence Support Portal - https://support.cadence.com
© 2019 Cadence Design Systems, Inc. All rights reserved w orldw ide. Page 22
Figure 25: Constraint Set from SigXplorer
10. The same constraint set will be seen assigned to the DAC_CLOCK net.
Figure 26: ECSet added to the DAC_CLOCK net
Note: Capture CM supports audit or apply for ECSet for the "Allegro Design
Entry CIS" license and higher versions.
