Allegro PCB Designer RAKs

Enabling CM Existing Design with Constraints Added in PCB Layout

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Enabling CM on Existing Schematic Design with Constraint Added in PCB Layout: RAK Learn more at Cadence Support Portal - https://support.cadence.com © 2019 Cadence Design Systems, Inc. All rights reserved w orldw ide. Page 17 Module 6: Viewing Topology using SigXp Flow You can assign constraints using the SigXp flow also. The SigXp flow allows you to view the topology of the signal flows. It also allows you to assign constraints like propagation delay and relative propagation delay. Note: The constraints assigned through the SigXp flow are through ECSets. ECSets are automatically assigned to the targeted nets after the constraint definition. 1. Open the CM UI. Select the DAC_CLOCK net. Do an RMB-click and select SigXplorer. Figure 19: Launch SigXplorer 2. Select OrCAD PCB SI from the Product Choices dialog box.

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