Allegro PCB Designer RAKs

Enabling CM Existing Design with Constraints Added in PCB Layout

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Enabling CM on Existing Schematic Design with Constraint Added in PCB Layout: RAK Learn more at Cadence Support Portal - https://support.cadence.com © 2019 Cadence Design Systems, Inc. All rights reserved w orldw ide. Page 15 Module 5: Creating Pin Pairs A pin pair represents a pair of logically connected pins, often a driver-receiver connection. Pin pairs may not be directly connected but they must exist on the same net or XNet. Pin pairs are used to capture specific pin-to-pin constraints for a net or an XNet. You can also use pin pairs to capture generic pin-to-pin constraints for CSets. Generic pin pairs are used to automatically define net- or XNet-specific pin pairs when CSet is referenced. 1. In CM, navigate to Min/Max Propagation Delays and select the K-LINE XNet. Do an RMB to select Create > Pin Pair. Figure 16: Pin pair creation 2. In the Create Pin Pairs of K-LINE dialog, select J5.5 as the first pin and U30.4 (ln) as the second pin. Click Apply.

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