Cadence Videos

  • Scribble Routing - OrCAD Product Feature1:25

    Scribble Routing - OrCAD Product Feature

    Scribble is a simple routing mode that allows you to ‘draw’ a route path for the trace to automatically follow. It provides a quick two-pick methodology to generate complex route paths, along with ver

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  • Manufacturing Solution Overview1:32

    Manufacturing Solution Overview

    Working with your manufacturer and setting up your fabrication, assembly and testing checks from the beginning can help you easily identify and avoid any unexpected problems before they disrupt your p

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  • Allegro - DFM (DFF-DFA)2:10

    Allegro - DFM (DFF-DFA)

    Checking for DFM issues DRC violations are shown in the design canvas in real-time while designing, because the best time to find and fix errors as well as a faster completion time for the designs.

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  • Advanced Route Analysis Solution1:20

    Advanced Route Analysis Solution

    Improve PCB design quality by identifying and optimizing various routing configurations. Utilize 9 user configurable checks to; locate, identify, and adjust your design.

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  • High-Speed - High Density Interconnection Solution1:12

    High-Speed - High Density Interconnection Solution

    Learn how to utilize blind, buried and micro vias to save space and pack power in a more compact HDI design.

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  • Exclusive DesignTrue DFM Solution2:07

    Exclusive DesignTrue DFM Solution

    Identifying potential problems before you finish the design and before you begin the manufacturing process helps reduce costs and eliminate added expenses.

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  • Team Design Solution - Symphony Overview1:29

    Team Design Solution - Symphony Overview

    Symphony allows multiple PCB designers to easily work on a shared design at the same time in real-time, and any changes made by one team member are seen by all members on the session.

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  • Understanding W-Element Transmission Line Model for Pre-Layout Parallel Bus in SystemSI8:28

    Understanding W-Element Transmission Line Model for Pre-Layout Parallel Bus in SystemSI

    Explaining different components of the W-Element transmission line model, such as the MCP (model connection protocol) section and RLGC matrices, generated by the TLine Editor.

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  • Understanding Transmitter and Receiver AMI Model Parameters of Serial Link Systems in SystemSI19:57

    Understanding Transmitter and Receiver AMI Model Parameters of Serial Link Systems in SystemSI

    Demonstrating the step-by-step process of setting values of several parameters in the property form of AMI blocks of transmitter and receiver of a serial link system (SLS) in SystemSI, followed by def

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  • Understanding Simulation Analysis Parameters for Serial Link Systems in SystemSI22:05

    Understanding Simulation Analysis Parameters for Serial Link Systems in SystemSI

    Demonstrating the step-by-step process of setting parameters in the analysis options form and property form of the transmitter and receiver of a serial link system (SLS) followed by definition and pur

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  • Understanding Simulation Analysis Parameters for DDR4 Bus Systems in SystemSI16:51

    Understanding Simulation Analysis Parameters for DDR4 Bus Systems in SystemSI

    Demonstrating the step-by-step process of setting timing budget, jitter and several other parameters in the analysis options form, before simulating a DDR4 interface of a layout file, using the System

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  • Understanding Process of Generating Ports in PowerSI15:02

    Understanding Process of Generating Ports in PowerSI

    Demonstration of the step-by-step process for generating ports automatically/manually for extracting S-parameters model of the the power-aware parallel bus interface of a layout file, using PowerSI.

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  • Understanding PowerSI Generated S-parameters and Circuit Files34:32

    Understanding PowerSI Generated S-parameters and Circuit Files

    Explaining formats and contents of Touchstone and BNP S-parameters data files and circuit files, generated at the completion of the simulation of a layout file in PowerSI.

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  • Understanding Model Connection Protocol in Circuit Files of Blocks in SystemSI8:51

    Understanding Model Connection Protocol in Circuit Files of Blocks in SystemSI

    Demonstrating the step-by-step process of viewing and understanding model connection protocol (MCP) section, generated by default, in circuit files of controller and memory blocks of a parallel bus sy

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  • Understanding EYE, BER and BATHTUB Plots from DDR4 System Simulation18:39

    Understanding EYE, BER and BATHTUB Plots from DDR4 System Simulation

    Demonstrating the step-by-step process of generating 2D plots, Eye diagram, BER and Bathtub plots, based on the sweep mode simulations of a DDR4 interface, using the SystemSI-PBA tool and then explain

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  • System Capture - Importing a Block in Read Only Mode3:48

    System Capture - Importing a Block in Read Only Mode

    This video shows you how to import a read-only block.

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  • System Capture - Creating a Design Variant5:19

    System Capture - Creating a Design Variant

    This video shows you how to create a design variant.

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  • Creating DRC Markers in the PCB Editor with SKILL5:37

    Creating DRC Markers in the PCB Editor with SKILL

    The PCB Editor SKILL API provides the axlDBCreateExternalDRC() to allow you to programmatically add DRC markers to the PCB Editor database.

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  • The Allegro PCB Editor SKILL Selection Mechanism7:00

    The Allegro PCB Editor SKILL Selection Mechanism

    ​The PCB Editor SKILL API includes functions that allow you to programmatically select elements for processing using the same mechanism that is used for standard PCB Editor commands. In general, when

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  • Adding Elements to the PCB Editor Database with SKILL5:24

    Adding Elements to the PCB Editor Database with SKILL

    The PCB Editor SKILL API includes a set of axlDBCreate() functions that are used to add new elements to the PCB Editor database.

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