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Overview of Advanced Semiconductor Packaging

Land grid array

30-40 years ago, semiconductor packaging lacked a certain elegance. Younger engineers are familiar with the DIP packages they used in lab classes, but that style was formerly the standard packaging used for most components. Once SMD packaging became mainstream, and the standard assembly processes were able to provide the required quality and yield, semiconductor packaging for SMD components has seen continuous innovation that continues to this day.

Advanced packaging for semiconductors has focused a variety of methods for expanding functionality, and has even gone in the direction of modular chip packaging design. Together with advanced semiconductor processing capabilities, modern chip packaging also packs more features into smaller spaces by building chips in three dimensions.

Types of Advanced Semiconductor Packaging

Today, packaging comes in many varieties, ranging from the traditional single-die chip or flipchip with wirebonding, up to advanced products integrating multiple chipsets in a modular fashion. Design tools have been available to build a variety of packaging structures for the past three decades, but these have only recently been used at scale to design advanced ASICs, processors, and highly integrated SoCs/SIPs.

In addition to market pressure to pack more functionality into smaller devices, this trend is being driven by the concept of heterogeneous integration. The concept is even outlined in IEEE Electronics Packaging Society’s (EPS) Heterogeneous Integration Roadmap. In this packaging methodology, designers take multiple components, which could be supplied by different vendors, and combine them into a single package on top of a substrate and interconnect structure.

Interposer + Substrate

The foundational piece that makes advanced packaging possible is interposers. These thin substrates provide a base where individual dies will be placed, as well as tiny interconnects to attach to the main packaging substrate. Interposers used in these advanced packages are made of three possible materials:

  • Silicon, which uses through-silicon vias (TSVs) to form connections to the package substrate
  • An organic material, sometimes called the organic redistribution layer (RDL)
  • Glass, which has become desirable in some of the newest advanced products

Silicon interposer

Although glass is known to be very useful for wideband heterogeneously integrated products operating at very high frequencies (around 100 GHz), silicon has an additional benefit as an interposer. Silicon interposers can be active, meaning they are part of the device fabric and can contain circuits built into the interposer.

If you think about it, an interposer performs a similar function as a PCB. Even though the interposer is planar like a PCB, and it uses vertical interconnects to pass between layers, most PCB and IC design tools are not capable of performing the necessary design and analysis tasks needed to build interposers.

Flipchips, 2.5D Integration, and 3D Integration

2.5D integration, and later 3D integration, arose from a desire to reduce integrated package sizes. This began with flipchips (see the conceptual image below), which were attached to a substrate directly or with wirebonding. Getting flipchip packages to scale to smaller sizes required placing dies side-by-side (2.5D integration), or as well as top of each other (3D integration), so that overall package size can be decreased.

This packaging type also integrates multiple dies or chiplets on top of an substrate + interposer structure in 2D or 3D. In 2.5D, the overall structure builds vertically, but dies/chiplets are not stacked vertically. In 3D, we can have the same substrate + interposer, but groups of dies may be stacked in 3D. The graphic below compares these packaging types.

Heterogeneous integration

Left: Flipchip packaging concept. Center: 2.5D integration on an interposer. Right: 3D integration on an interposer.

The interposer plays two important roles in  2.5D and 3D integrated packages:

  1. By packing everything into a single interposer + substrate system, the interconnects are physically smaller. This means lower parasitics and data transfer at high speeds with better signal integrity.
  2. The interposer can reduce the number of signals that need to leave the package simply because more of the important supporting components are built into the package. This means the layout of these systems could be simplified, depending on how the component is designed.

These factors do not always simplify the process of designing assemblies with advanced packaging. Instead, it shifts that complexity onto the packaging designer. Depending on the number of I/Os available on the component, the BGA or LGA footprint for these packages can still be very large with fine pitch. The standard set of best practices for placing and routing into BGAs/LGAs will still need to be implemented in the PCB layout.

Package-on-Package (PoP)

The package-on-package (PoP) concept is similar to a set of stacked BGAs. Multiple packages are constructed with BGA footprint and stacked vertically on successive substrate layers. In theory, this allows an existing package to be integrated directly on top of another package, similar to stacking multiple PCBs on top of each other. The lowest level ball array is soldered to a PCB and provide access to the remaining portions of the package.

Package-on-package structure

Package-on-package concept

System-in-Package (SIP)

This is less of a specific packaging structure and more of a design methodology or type of packaging design. All systems-in-package (SIPs) follow a specific design concept: the package attempts to integrate as many components as possible so that the package contains an entire system, often being designed for a specific application.

Any of the following elements can be present in SIPs for advanced components:

  • Memories, including high-bandwidth memory
  • RF or analog interfaces
  • Power management blocks
  • One or more processing cores
  • Specialty DSP blocks for specific applications

Some newer components are being designed as SIPs or SoCs with advanced reconfigurable logic, meaning an FPGA coprocessor is implemented in the package. This gives the component designer significant flexibility to tailor an SIP to their end product, as well create a caveat for later reconfigurability once the product is deployed in the field.

System in package

Finally, there is sometimes a distinction made between a system-on-chip (SoC) and an SIP. An SoC is still an SIP, but it only exists as a single chip, which may not be designed as an interposer. For this reason, you might see some SoC products placed in traditional packaging or in integrated packaging with an interposer and substrate. SIPs also provide the integration seen in SoCs, but they implement the type of integration with multiple components outlined above.

No matter what type of advanced semiconductor packaging is used for your components, you can deliver the automation and accuracy with Allegro X Advanced Package Designer from Cadence. 

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