OrCAD datasheets

OrCAD PCB SI 2 OrCAD PCB SI delivers powerful simulation technology to help you find and address signal integrity issues throughout the design process SI environment enables you to explore different what-if scenarios to determine the effects of different routing topologies, termi- nation strategies, component values, and placement. Pre-layout analysis Pre-layout analysis allows you to proactively explore interconnect scenarios and simulate critical nets to minimize signal integrity problems early in the design cycle during circuit definition and schematic entry. Utilizing the tightly integrated schematic entry and signal integrity flow between OrCAD Capture and OrCAD PCB SI allows you to define optimized clock and critical signal topologies, termination components, and values, as well as routing strategies, constraints, and board stack-up requirements for layout. Once you've decided on an optimal interconnect solution, a comprehensive set of design rules and constraints is defined to drive the physical design process. Post-layout analysis OrCAD PCB Editor provides you with the ability to extract topologies directly from the PCB design database, enabling you to simulate critical nets to validate that the layout work matches the pre-route requirements. Topology extraction can be performed at three key stages for signal quality analysis: during part placement, after routing critical nets, and after final routing of the design. Topologies are extracted into the same SI canvas that was used to analyze the net during pre-route, and the routed signal's analysis is compared to the expected results. The extraction includes a detailed electrical representation of how the net was physically implemented, including models for trace cross-sectional characteristics, routing layers, via models, and trace lengths. If the results do not match, the routed board can be modified and the net re-analyzed. Topology canvas and data display OrCAD PCB SI is comprised of two primary environments: Signal Explorer and SigWave. The Signal Explorer canvas provides an electrical topology view of the physical or logical interconnect and is the simulation cockpit for analysis of high-speed or critical nets. With Signal Explorer, you begin circuit exploration with various stripline and microstrip models (lossy or lossless), drivers and receivers, and devices. Imported circuit topology, either from OrCAD Capture or OrCAD PCB Editor, is also presented in this canvas for exploration and analysis. The SigWave canvas is the waveform viewer to display simulation results in multiple formats and modes. The oscilloscope mode allows the display of individual waveforms on and off, and provides markers for on-screen measurement. Model Integrity The Model Integrity module provides an editing environment within OrCAD PCB SI that allows the creation, manipulation, and validation of models quickly and easily. This module includes a model browser and syntax checker for models written in IBIS, as well as for advanced models written in DML. OrCAD PCB SI accepts device models from a variety of digital modeling formats—including support for the IBIS modeling standard— which means models created by most semiconductor manufac- turers can be used. In addition, OrCAD PCB SI supports the DML modeling format, a next-generation modeling language for more complex devices. This flexible macro-modeling extension language augments IBIS and allows state-of-the-art I/O function- ality to be modeled quickly and accurately. Signal Integrity Solutions and Flows Capture/PCB SI flow Tightly integrated to provide a bi-directional schematic entry and signal integrity flow, OrCAD Capture and OrCAD PCB SI allow you to perform circuit topology exploration, constraint devel- opment, and signal integrity analysis from the schematic during design entry. The associated Electrical Constraint set (Electrical CSet) as well as the complete topology file is embedded in the schematic database. PCB Editor/PCB SI flow Routed or unrouted topologies can be extracted directly from the PCB design database, enabling you to simulate critical nets to validate that the layout work matches the pre-route require- ments. Topology extraction can be performed at three key stages for signal quality analysis: during part placement, after routing critical nets, and after final routing of the design. Topologies are extracted back into the same SI canvas that was used to analyze the net during pre-route, and the routed signal's analysis is compared to the expected results. The extraction includes a detailed electrical representation of how the net was physically implemented, including models for trace cross-sectional charac- teristics, routing layers, via models, and trace lengths. If the results do not match, the routed board can be modified and the net re-analyzed.

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