Issue link: https://resources.pcb.cadence.com/i/1544351
Relative propagation delay applies for Match Groups that need to be length matched within their local group of signals. For instance, if we have signals for DDR like DDR_DQ0-DDR_DQ7 and they all need to have their signals arrive within 15 picoseconds of one another or less. There is a way to let the Constraint Manager know this. In Constraint Manager, in the Electrical category, go to your Net > Relative Propagation Delay worksheet. Highlight the nets you want to add to a matching group (i.e. DDR_DQ0 through DDR_DQ7, for 8 bit), then right click, Create – Match Group… Give the match group a name. Then click Ok. You will get the following image below and the option to change what Constraint Manager cares to constrain. 53 www.cadence.com OrCAD X Constraint Management Guide