PSpice Application Notes

DC-DC Converter Design Application Note

Issue link: https://resources.pcb.cadence.com/i/1543417

Contents of this Issue

Navigation

Page 11 of 12

Designing for Efficiency 12 www.cadence.com Using the same cursor window for both Si and SiC simulations is critical for valid comparison. 9.7 Recording Loss Components Record the averaged values for: f Total efficiency f Switch loss f Diode loss f Input and output power These values form the loss budget used to compare device performance and correspond directly to the loss waveforms visible in Figure 2. The waveform viewer allows direct export of numerical results or manual recording of averaged values. 9.8 Repeating for the Alternate Device Configuration Repeat Sections 9.2 through 9.7 using the alternate simulation profile. Ensure that: f The same cursor interval is used f No simulation parameters are modified between runs This guarantees an apples-to-apples comparison of waveform behavior illustrated in Figure 2. 9.9 Verifying Consistency After both simulations: f Compare steady-state waveforms f Confirm identical operating conditions f Verify that differences appear only in device loss waveforms The steady-state waveform structure should match the behavior shown in Figure 2, with differences appearing primarily in switching and diode loss magnitudes. This confirms that efficiency changes originate from semiconductor behavior rather than setup variation. 9.10 Troubleshooting Simulation Issues Switching power converters are numerically demanding to simulate because they combine fast transitions, nonlinear device models, and magnetic elements. If simulation results differ significantly from the steady-state behavior shown in Figure 2, the following checks resolve most issues. Convergence Problems Convergence warnings or simulation failure often occur when switching transitions are too abrupt or when initial operating conditions are poorly defined. If convergence errors occur: f Verify that all device models are correctly loaded and resolved f Ensure that no floating nodes exist in the schematic f Add small parasitic resistances to ideal inductors or voltage sources if necessary f Use consistent initial conditions across both Si and SiC simulations f If required, enable the simulator's convergence aids identically in both profiles The goal is to stabilize the physical model so that both configurations reproduce the expected waveform behavior.

Articles in this issue

Links on this page

view archives of PSpice Application Notes - DC-DC Converter Design Application Note