Examples of Signal Integrity Limits:
1. Timing Requirements:
Clock Skew:
ɢ Pass: < ±50ps
ɢ Warning: 50-75ps
ɢ Fail: > 75ps
Setup/Hold Times:
ɢ Pass: > 125ps setup, > 100ps hold
ɢ Fail: Below these limits
2. Crosstalk Limits:
Clock Signals:
ɢ Acceptable: < 8% coupling
ɢ Warning: 8-10%
ɢ Critical: > 10%
Data Signals:
ɢ Acceptable: < 10%
ɢ Warning: 10-15%
ɢ Critical: > 15%
7 www.cadence.com
OrCAD X High-Speed Digital Design Guide
