3. Minimize Inductance:
a. Route power traces with minimal loop area by keeping them parallel to ground traces
b. Use multiple vias for power connections to reduce inductance
c. Ensure short and wide traces for power delivery
4. Perform Power Integrity Analysis:
a. Use a power integrity analysis tool such as Celsius PowerDC to analyze the power distribution on a PCB
Example of Power Distribution Acceptance Criteria:
Core Power (1.2V):
ɢ Good: < 3% drop (< 36mV)
ɢ Marginal: 3-5% drop
ɢ Unacceptable: > 5% drop
DDR3 Power (1.5V):
ɢ Good: < 4% drop (< 60mV)
ɢ Marginal: 4-6% drop
ɢ Unacceptable: > 6% drop
15 www.cadence.com
OrCAD X High-Speed Digital Design Guide
