Issue link: https://resources.pcb.cadence.com/i/1534760
As you work within the Topology Workbench you will discover that you can vary the information, bits and pulses sent through the transmitter for the signal in that net as well, thus being able to test and search for any specific bit patterns that can come from the clock signal that can ruin the design. Depending on your findings from simulation, you can also back-propagate the appropriate constraints that would meet optimal signal perforce from the simulation. Then use those new constraints in OrCAD X Presto PCB Editor Constraint Manager to properly constrain the traces and PCB layout in a way that would comply with the desired simulation outcome. This is results driven and constraints driven PCB Design. For more information on how to use the Topology Workbench, refer to Cadence documentation and design guides. Power Integrity Considerations Power integrity (PI) is essential in high-speed PCB design, ensuring that power is delivered consistently and cleanly to all components. For our FPGA with DDR2 and DDR3 memory project, maintaining PI is critical to avoid voltage fluctuations and ensure stable operation. Proper PI considerations help prevent issues such as power noise and voltage drop, which can affect signal integrity and overall device performance. General Solution: Effective power integrity management involves designing a robust power distribution network (PDN), strategically placing decoupling capacitors, and minimizing inductance in power delivery paths. These practices help maintain a stable voltage supply across the board, even under dynamic load conditions. Application in OrCAD X Presto: 1. Design the Power Distribution Network (PDN): a. Go to Tools > Cross Section to define power planes b. Ensure dedicated power planes are included for core, I/O, and DDR3 voltages c. Set power planes within the stack-up to create low-impedance paths for power delivery. See the stack up below 13 www.cadence.com OrCAD X High-Speed Digital Design Guide