Steps/Example:
1. Open the Constraint Manager.
2. First, ensure that the Constraint Manager is analyzing all the electrical constraints, pin delays, etc., with Analysis Mode
enabled (from the menu select Analyze > Analysis Mode, choose all options in Electrical then click Apply and Okay).
3. Then navigate to this worksheet: Electrical > Net > Relative Propagation Delay.
4. In your design you will need to create a matched group for nets that are carrying parallel signals, like in the image below
where DDR_DQ(32) has 32 nets.
5. But first, make a pin pair for all the nets you want to put into a matched group. For example, let's say you didn't have the
DDR_DQ# signals in a match group yet. You would select something like the DDR_DQ0, right click it - Create > Pin Pair…,
click Ok when presented with the pin options.
6. Once done, that will create the pin pair underneath the signal in the worksheet (shown below).
7. Where it says All Driver/All Receivers, you can change the pin pair relationships to other options such as:
a. Longest Pin Pair
b. Longest Driver/Receiver
c. All Drivers/All Receivers
d. (Clear)
8. For this example, we selected All Drivers/All Receivers. After that, you repeat the previous steps to create more pin
paired nets, then to put your nets into a matched group.
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OrCAD X High-Speed Digital Design Guide
