Impact:
The signals propagating through the differential pairs are in sync in real time and at the receiver. Proper control over the
traces for in sync signal behavior reduces noise created from common mode voltages and improves signal timing for
high-speed data transmission.
Other High-Speed Constraints
Wiring Topology
Set specific routing paths for technologies such as DDR3 to optimize for their signal and power needs. Common topologies
include Daisy Chain, Star, and T-branch.
Diagram showing the prioritized routing of critical nets on a PCB.
Definition: Wiring topology involves organizing the connections between different nets on a PCB to achieve a certain
outcome, such as minimizing signal reflections, signal attenuation or voltage drops.
Example: Let's ensure that a pulse-width modulated net follows a daisy-chain topology.
70 www.cadence.com
OrCAD X High-Speed Digital Design Guide
