PCB Layout
Introduction
PCB layout is a critical phase in high-speed design, where the schematic and constraints are transformed into a physical
board. For our FPGA with DDR memory project, careful attention to component placement, stackup definition, and routing is
essential to maintain signal integrity and meet performance requirements.
This project has a completed PCB layout. We will analyze the critical parts of the design that need to be created for a
successful high-speed layout. Not every net will be covered in this design. We will explain just enough of the nets and rules to
implement so you know how to apply them to most any situation. The rest of the net or entire design is left as an exercise for
the reader.
Top view of a completed PCB Layout.
Here are the devices we will focus on:
f
FPGA
ɢ Manufacturer Part Number: XC6SLX25-3FTG256I
f
2 DDR3 interfaces
ɢ Manufacturer Part Number: UPD431000AGW-B15
ɢ Manufacturer Part Number: MT41J512M4JE-15E:A
The operating frequency for DDR interface is 300–800 MHz, maximum allowed jitter could be whatever is reasonable,
crosstalk coupling limit 8% for critical signals like clock, target impedance for power distribution network, and a FCC class
- whichever one is more lenient.
Manufacturing capabilities specify a minimum trace width of 4 mils for high-speed signals. Standard non-high-speed signals
are maybe 6 mils. There is a lot going on in the design, but we will start with the most essential high-speed signals and steps
in general that need to be covered.
43 www.cadence.com
OrCAD X High-Speed Digital Design Guide
