Then apply it to the appropriate differential pairs in the Net > All Layers worksheet. Expand the PCI_PAIRS Net Class (shown
below), then apply it to any of the differential pairs within that class, like PER0. Notice that the rule is applied to all the differ-
ential pairs within that class already.
Spacing Constraints
We can even set spacing constraints at the schematic phase. Proper spacing is critical to avoid crosstalk in PCB design. The
general most conservative rule of thumb is to make the trace edges at least 3 times the width of any particular trace. In some
cases, it can be less than or more than that. The details are left up to your discretion from design guides, datasheets and EMC
specialists.
To separate the standard traces from each other and maintain minimal coupling in general, we create the following:
1. Critical Signal Spacing:
a. CLK to other signals: 3x trace width
b. DATA to DATA: 2x trace width
c. ADDR to ADDR: 1.5x trace width
2. BGA Region Specific:
a. Trace to Trace: 4 mils
b. Pad to Trace: 5 mils
c. Via to Via: 8 mils
3. Differential Pair Spacing:
a. Intra-pair spacing
b. Inter-pair spacing
35 www.cadence.com
OrCAD X High-Speed Digital Design Guide
