2. Then assign this constraint set by going to the Net > Routing > Total Etch Length worksheet.
3. Then assign the constraint, PCI_DIFF, on the STDA_SSRX Differential Pair object as shown below.
Electrical Constraints Conclusion
By meticulously defining constraints within the Constraint Manager, we've established a robust framework for our high-speed
FPGA design.
These constraints will guide the PCB layout process, ensuring that critical signals meet their performance requirements and
that the design adheres to manufacturing standards.
In the next section, we'll explore how to apply these constraints effectively during the PCB layout phase, translating our
defined rules into a physical design that meets our high-speed requirements.
Physical Constraints (Schematic Phase)
First, we'll create a physical constraint set for our DDR3 interface using the Constraint Manager. The physical constraints for
the PCB are set by current carrying capacity, board density, manufacturable capabilities of your manufacturer, and
impedance abilities of the selected materials for your PCB stack-up. For our design we have the following constraints as
examples.
Trace Width Rules:
f
Minimum width: 4 mils (high-speed signals)
f
Standard width: 6 mils
f
Neck Mode: 3.5 mils (BGA escape)
Differential Pairs:
f
Min Line Spacing: 3.5 mils
f
Trace Width: 4 mils
f
Gap Width: 3.8 mils
f
Max Uncoupled: 100 mils
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OrCAD X High-Speed Digital Design Guide
