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2. Decoupling capacitors: Strategic placement of decoupling capacitors provides local energy storage and helps to filter out high-frequency noise. a. Decoupling and bypass capacitors must be placed close to their respective voltage sources and device pins to effectively manage power and prevent voltage rail collapse and ground bounce. b. Also where possible, use smaller capacitor package types (0402 and 0201 vs 0603 and 0805) because they have smaller leads and therefore lower inductance and impedance. 3. Grounding strategy: A well-designed grounding scheme minimizes ground loops and noise coupling. To achieve proper grounding, you need to create star-based ground connections, so place fanouts to ground and power from each of your parts' pins to allow individual return paths to ground and source paths from power for maximum current carrying capacity. PDN as a Network of Parasitics: The PDN can be modeled as a complex network of parasitic capacitors, inductors, and resistors distributed throughout the PCB layout. By following best practices mentioned in the previous numbered list and applying PDN design principles, you can create a robust power delivery system that ensures the reliable operation of your circuit. The best way to truly analyze the power distribution network is through simulation and discovery of overall PCB noise when its combined impedances are joined together and multiplied by the currents running through the entire board. While a precise equation for PDN analysis isn't practical due to the complexity of the interactions (we need multiple equations), a generalized approach can be represented as: PDN Noise = (Combined Impedance of PDN) × (Currents through the PCB) Key Points: f Combined Impedance of PDN: This encompasses the resistance, inductance, and capacitance of all elements within the power distribution network, including planes, traces, vias, and decoupling capacitors. f Currents through the PCB: These are the currents drawn by all active components on the board. Impedance Considerations: f Resistance: Primarily determined by the resistivity of the conductors and the geometry of the traces and planes. Reduce resistance in your conductive material by using smoother materials (speak with your manufacturer) since ragged edges increase resistance through heat and the skin effect. f Inductance: Influenced by the loop area formed by current paths and the presence of vias. Minimize loop area as much as possible with short, wide traces and large copper pour. f Capacitance: Affected by the spacing between conductors, dielectric materials, and the presence of decoupling capacitors. Therefore, keep conductive layers of your PCB as close as possible for your manufacturer, to maximize capacitive coupling between traces and their reference planes, and from plane to plane capacitance. Increased capacitance lowers impedance and therefore reduces noise created by current and voltage. Impedance: Z = R + X L +X C Voltage: V = I x Z Where Z is the impedance of the PCB traces at any given location and over some area, I is the current running through the traces and V is the voltage generated by the current going through said traces and component terminals. This voltage generated applies not only to all your voltages on the PCB but any noise on the 'zero reference' that we usually call 'ground' (it has a voltage, even though it's close to 'zero') as well. 10 www.cadence.com OrCAD X High-Speed Digital Design Guide