Issue link: https://resources.pcb.cadence.com/i/1533024
For the minimum or maximum, a number value is provided as the upper and lower limits. I find the Total Etch Length constraint is helpful for getting into the ballpark where all the traces are between the minimum and maximum. From there, the relative propagation delay rule will help resolve a better length match. You can center-cut the meter so all lines end up essentially the same exact length. This fine tuning along with rounded off corners will make the Signal Integrity people want to have you on their jobs every time. Figure 7. Here, we have created the I2C match group and want to add timing rules. The arrow near top center indicates where a trace (red) is being lengthened to match the two green ones. To the right, you see the meters. A differential pair would have another meter that indicates the status of the phase matching. This one shows a three segment meter for the length relative to the designated clock. In this case, the system selected TDO as the clock. A right mouse click in the Delta:Tolerance column allows us to pick a new clock such as TCLK in this case. Below is a two segment meter that controls the maximum length to a set number. A minimum length can also be applied which helps resolve a match group by providing more context. This isn't meant to be a comprehensive tutorial but more of an overview of the constraint manager. We've covered parts of the Physical, Spacing and Electrical worksheets. The Same Net Spacing works much like normal spacing but only as it relates to objects of the same net. The thrust of this constraint is to avoid air gaps that are not producible but would not otherwise be flagged as a short. The manufacturing worksheet is broadly focused on DFx issues. We went over the placement function in the first section. Meanwhile, the fabrication sheet is a way to generate hard-stop air gaps between features. These values are oftentimes straight from the fabricator's capabilities literature. The idea is that these are a baseline minimum while there are probably larger air gaps in play for other reasons. The DFM rules are more of a backstop, an ultimate limit. The actual spacing rules will hopefully be more conservative everywhere except within special regions for HDI or UHDI. The reader is encouraged to poke around. The scope here is to shed some light on the constraint manager to get you going. There are deeper dives on the Cadence website and in Help documentation along with useful videos on YouTube that provide easy wins when you need to know how something works in detail. It takes some doing to set up constraints but the reward is in how efficient it becomes to deliver compliant PCB designs on time. When it comes down to crunch-time, a good set of constraints will guide you to the hoped for result; a win. 7 www.cadence.com Controlling Trace Length for Digital Circuits Using OrCAD X and Allegro X Tools