The 1 mil lines representing the bond wire would be removed from the etch layer so that the fan-out can be completed on that
layer. I use Layer 1 to "route" bond wires for the line lock so that the 45 degree maximum launch angle is locked in. Further, the
wire length should not exceed 100 times the diameter so a max length could be enforced as well. We will get to that next. You
can really go deep with constraint regions inside of constraint regions as you work from the chip to the wirebond cage to the
outer areas of the board or substrate.
Figure 7. The Inter Layer Spacing window is almost too big for my 5K monitor. This is a sprawling check box field where I'm currently selecting
the square to add a rule between the Stiffener_Top layer and the Bend_Line layer. I chose to add a gap of 1. 6 mm. There is a separate
window from this one focused on managing metal layers.
So, that's all I have space for today. This is likely the first design rule you're going to want to solve in most cases. The spacing
rules take time to grow into your flow. The standard rule set may be all you need. Get ready for the next dimension. The 4th
dimension. The Electrical Constraint Set and how the timing budget on the PCB affects the system level performance. Part
Four awaits.
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Controlling Air Gaps Using OrCAD X and Allegro X Tools
