OrCAD X Resources

Controlling Trace Width Using OrCAD X and Allegro X Tools Discussions of copper width and thickness are drawn from power and impedance requirements. These have to be filtered through the lens of what can be done by your fabricator's production limitations. We have to pull data in for thermal consider- ations. Every part has a rating that it has to meet. Provisions for dissipating the expected heat build-up have to be included on the board. For the most part, we rely on what can be found in the schematic to help us set up design rules for signal integrity. For things that we can't discover for ourselves, engage with the cognizant engineer who is driving the project. They will know what is most important but there may be some disagreement if you're part of a team project where people are competing for the most valuable PCB real estate. When the inevitable conflict arises, the written correspondence should carry more weight than spoken words. Of course, it always depends on whose words are in play. Either way, what is written is going to reflect what is done. The most useful callout is noting the impedance on the schematic page while embedding the impedance value as an attribute given to the net(s). That would be nice. Of course, the name of the net(s) should also provide context for capturing the high-level design rules. Without those clues, you'll rely on standards, component datasheets and application notes to provide the general guidelines along with all of the pin functions. Knowing which traces get the treatment is only the start. Parsing that information into line geometry and dielectric thickness is part of your gig. The stack-up data and the constraint manager work together to form the virtual twin that drives the production of boards. There are tools that allow us to easily calculate stripline or microstrip models. The best data to use is the stuff you get from the fab shop that is going to eventually build your boards. The usual flow is to take a shot at it yourself first. Propose a line width and stack-up to your vendor(s). They respond with something close to that but using numbers for the dielectric constant based on the material they use. That can vary by country but also by which of numerous PCB factories will be used by the ODM as you go to mass production. This vendor feedback often requires a small update to your proposal. Depending on your relationship with your vendor (or the internal buyer) they may be up for generating the stack-up and all of the controlled impedance geometry layer by layer. This is really nice to have at the beginning of a project. I have to say that there is also a school of thought where you give them your nominal data and describe what each line width means in terms of impedance. They give you the feedback and as part of the DFM cycle, you approve the deviations between the artwork and the physical board. If I'm using multiple vendors for a job, I'm likely to take this course. After working with a manager who saw technical questions from the vendor as a failure of the ECAD designer, I want to minimize the post-tape-out interactions. If you can get ahead by capturing the actual data ahead of time, it's worth the effort. The easiest way to get traction with a constraint set is to start with a mature board and export those constraints. In order to read it into the new database, the names of all of the etch layers must match. After enough years of doing this, I have some 8, 10 and 12 layer scripts that clean up old "vendor" designs so that they comply with layer naming standards. There will still be specific attributes to capture that align with the net names and other conventions of the current project. 2 www.cadence.com Controlling Trace Width Using OrCAD X and Allegro X Tools

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