Issue link: https://resources.pcb.cadence.com/i/1533022
The physical parameters also include the type of via to use. As an example, the BGA field in the Figure 1 image is populated with smaller vias than those outside. Support for stacking or staggering blind and buried vias is also supported in this window along with a true/false option that restricts routing to certain layers. The constraint manager spreadsheet is just too wide to show it all clearly. The physical constraints are parsed three ways with the general rules first followed by net-specific details. The typical "detail" is selecting what type of trace technology to use from the general classifications but there are many options for constraining traces. Minimum Width is straightforward. The only issue is that it has to be less than the maximum - unless the maximum is set to zero. The zero means that there is no maximum so whatever width you choose in the PCB editor is allowable by the Design Rule Checker (DRC) just as long as it meets the minimum trace width. The third method of width control, beyond default and neck down, is to use a constraint region as mentioned above. When I really want to control the line width for a trace on a given layer, I will set the Minimum, Maximum, and Neck width to the same value. If the line is any other width for a connection on that layer, a DRC flag will appear until the line is changed to the one and only value being allowed. Taking this step allows us to prove that the RF traces are all the same as the specified width. The Physical Constraint Set has to have the same value in all three locations for the Minimum, Maximum and Neck modes. This is most important when you're making a global change to the trace geometry and do not want to leave anything behind. Figure 2. This is the "Net" folder of the Physical Constraint set.The red box now indicates the location for the Right-Mouse-Click to add a net (or three selected nets in this case) to a bus. Different tabs of the constraint manager allow for the creation of different types of groups depending on context. To the right you see the filter for simplifying the results. Creating "rooms" for component placement is a good way of keeping component groups together. This method goes beyond what is in the group to include defining where the group would be placed on the board. The rooms can have assigned values for maximum height which would be useful for groups that live inside of a shield or other low headroom area. Of course, those areas are ripe for getting their own set of local design rules as well. We set up the high level placement, known as floorplanning using critical routing and voltage domains as guidance. Floorplanning generally starts with the components in predefined locations, say connectors and heatsinks for example. Then, the larger integrated circuits are considered. For smaller circuits such as regulators, I like to create an ideal layout of the section off to the side of the board for a more informed placement before I bring that circuit onto the board. 4 www.cadence.com Controlling Trace Width Using OrCAD X and Allegro X Tools