Issue link: https://resources.pcb.cadence.com/i/1533021
Having come from Qualcomm, the minimum spacing I was used to was driven by the cell phone industry. Our component spacing was determined by the minimum soldermask web for the smallest parts. There was some agreement between Qualcomm and Google at that scale but Google's DFA rules required more room, particularly around the connectors and active devices. Figure 6. Using revised DFA values for a double sided HDI circuit circa 2014 In this case, I didn't have to edit the library symbols. What happened is that wherever the spacing value was above 250 microns (10 mils) would be changed to 250 microns. Values that were already lower than that would remain as they were. Just like that, the spacing rules were adapted from rack equipment down to that of a dongle. Given the chance to create more accurate 3D renders and exports along with the flexibility introduced by using the DFA option is too good to pass up. I had to make this the opening chapter of the story of how using design constraints can lead to high confidence in the board fabrication and assembly processes. Yes, there is a bit of work on the library to do up front. A good part of the effort is repetitive which means that a script could be written as the first footprint is updated. The next part would start out by playing back the script. Then all you do is check to see if anything needs to be tailored to that footprint before moving on to the next one. This may not seem like a high priority and it is not unless you are the official librarian. Most places will have a lull between product introductions where you need something productive to fill that downtime. 8 www.cadence.com Smart Placement Using Design for Assembly Tools