Issue link: https://resources.pcb.cadence.com/i/1526746
Now, you can make any kind of rule (e.g., a spacing rule) to apply to that group of nets. Let's create and apply that spacing rule. Let's say we want all USB nets, whether power or signal, to have a certain voltage withstanding by keeping them far enough away from other objects that might get to that high a voltage (10 mils/0.127 mm of clearance is sufficient for 500 V withstanding on the PCB surface according to IPC-2221B, Table 6-1). So, let's set a rule for 10 mils (0.254 mm) minimum spacing in the design. 11. With the CM still open, go to the Spacing Constraint Set - All Layers section. 12. Right-click the cell in the Dsn row named P3449_B01_Allegro_layout. 13. From the dropdown menu, select Create - Spacing CSet…. 14. The Create SpacingCSet window appears. 15. In the SpacingCSet field, name it SCS_USB, then click Ok. Tip: SCS means SpacingCSet, so we can distinguish that constraint set from others such as physical CSets (PCS) and electrical Csets (ECS). 16. You will see your spacing constraint rule set below. 15 www.cadence.com Part 1 of 5