OrCAD X Resources

OrCAD X DesignTrue DFM Rules Guide

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Cadence is a pivotal leader in electronic design and computational expertise, using their Intelligent System Design Strategy to turn design concepts into reality. Cadence customers are the world's most creative and innovative companies, delivering extraordinary electronic products from chips to boards to systems in the most dynamic market applications. www.cadence.com © 2024 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence, the Cadence logo, and the other Cadence marks found at www.cadence.com/go/trademarks are trademarks or registered trademarks of Cadence Design Systems, Inc. All other trademarks are the property of their respective owners. 05/24 BS/CPG-RG-DFM/PDF 5 - Test Point to All Non- Plated Holes Defines the minimum distance allowed between the center of a test point and a non-plated hole. (DFT_SPC_ TP_NPHL) Etch 6 - Test Point Under Component Flags a DRC if a test point is present under a component. (DFT_SPC_TP_UN_PKG) Etch 4. Core Probe DFT Constraint Set Index Ref Rule Description Usage Image 1 - Test Point Minimum Pad Size Defines the minimum pad size allowed for a test point. DRC is flagged if pad size of a test point is less than the specified value. (DFT_PR_MINPDSIZ) Etch

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