Design for Test Core Checks
The checks defined within this domain are focused on the design for the testability process. The rules aid in providing proper
clearances and other constraints to improve the test point access and reduction of issues related to testing.
1. Core Outline DFT Constraint Set
Index Ref Rule Description Usage Image
1 - Test Point to
Outline
Defines the minimum distance allowed between the
center of a test point and the design outline. (DFT_TP_
TO_OLN)
Etch
2 - Test Point to
Cutout
Defines the minimum distance allowed between the
center of a test point and a cutout. (DFT_TP_TO_COUT)
Etch
2. Core Mask and Silkscreen DFT Constraint Set
Index Ref Rule Description Usage Image
1 - Test Point on
Soldermask
Flags a DRC if soldermask is missing from a pin or a via
with a test point. (DFT_MSK_TP_MSNGMSK)
Non-Etch
2 - Test Point to
Silkscreen
Defines the minimum distance allowed between the
center of a test point and a silkscreen object. (DFT_TP_
TO_SS)
Non-Etch
3. Core Spacing DFT Constraint Set
Index Ref Rule Description Usage Image
1 - Test Point to
Test Point
Defines the minimum distance allowed between the
centers of two test points. (DFT_SPC_TP_TP)
Etch
2 - Test Point to
Component
Defines the minimum distance allowed between the
center of test point and a component. (DFT_SPC_TP_
PKG)
Etch
3 - Test Point to
All Pin Pads
Defines the minimum distance allowed between the
center of a test point and a pin pad. (DFT_SPC_TP_PNPD)
Etch
4 - Test Point to
All Via Pad
Defines the minimum distance allowed between the
center of a test point and a via pad. (DFT_SPC_TP_VIAPD)
Etch
17 www.cadence.com
OrCAD X DesignTrue DFM Rules Guide
