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Figure 11. Signal/Ground arrangement in D-SUB connectors; S=signal, G=ground.
We use a 2-D finite-element field solver to obtain the capacitance and inductance matrix:
L11=2.97 nH
L12=0.98 nH
L22=2.91 nH
C11=0.122 pF
C12=0.0314 pF
C22=0.122 pF
An 8 Lump RLCG model can be used such as TLUMP8. For simulation of crosstalk we can use
KCOUPLE2 or a lumped coupled model.
STEP 4: Simulate Net. Run a 150 ns transient analysis for the circuit of figure nn.
STEP 5: Compare results to design specifications.
It is extremely important for a system clock to meet the specifications for Vil,max and Vih,min at all
receiver inputs. If a "glitch" were to exceed these voltages, we risk the possibility of data corruption.
Figure 12. Voltage margins.
The Probe plot (figure 13) shows that Vih,min=-1.165mV and Vil,max=-1.475mVare never exceeded, and
the clock edges are monotonic through the transition region. The differential input voltage at the end of
the 30 ft cable is 382mV worst case, which exceeds the required minimum 300mV.
