25
Normal logic swing is about 800 millivolts.
Voh=-0.9 volts
Vol = -1.7 volts
Guaranteed noise margin:
High level, 125 millivolts
Low level, 125 millivolts
Although these are guaranteed minimums, each is generally better by about 75 millivolts.
Normally, Vcc is grounded and Vee is tied to –5.2 volts.
Typical risetime is 1 ns
Typical gate delay is 1 ns
Ouput Impedance is typically 5 ohms in both high and low state
Gate input impedance is typically 50 K-ohms
Gate input capacitance is typically 3-5 pF.
Gate output capacitance is typically 2-5 pF
Ouput pulldown resistors are not included on chip
Maximum recommended open line length for microstrip configuration
Z0 (ohms) Fanout=1
(3.3pF)
MAX IN.
Fanout=2
(6.6pF)
MAX IN.
Fanout=4
(13.2pF)
MAX IN.
Fanout=8
(26.4pF)
MAX IN.
50 1.6 1.1 0.7 0.6
68 1.4 0.8 0.5 0.4
75 1.3 0.8 0.4 0.3
Table 7. Maximum open line length for ECL 100K for microstrip.
In practice, there is a tradeoff between use of terminations and lowering power dissipation. Thus,
terminations are not perfect in the clock path.
STEP 2: Decide how to model the net.
The data path involves single-ended signals on the PCBs, and a differential signal through the 30 ft
ribbon cable. The following are also suggested by the schematic:
A typical model for ECL 100K is needed.
A multiconductor model is needed for the ribbon cable, since it will be driven differentially.
The PCB transmission lines must be characterized.
The board to board and board to cable connectors must be characterized. These models should
account for ground pin locations for a later crosstalk simulation.
