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Signal Quality Analysis of an ECL System Clock
This example serves to illustrate the process of modeling and simulating a high-speed system clock net,
by applying the steps outlined in the flowchart.
Introduction
A ECL system clock must pass through multiple PCBs (including backplanes), and a 30 ft cable. It is
desired that ribbon cable be used, but if necessary twinax can be used (although it is more expensive).
Figure 11. ECL system clock spanning multiple PCBs.
STEP 1: Determine driving frequencies and technology constraints.
We are using ECL100K technology, which has the following device characteristics:
