Cadence PCB success stories

NVIDIA and Cadence

Issue link:

Contents of this Issue


Page 0 of 2

The Customer NVIDIA leads the industry in developing visual computing technologies and is the inventor of the GPU, a high-performance processor that generates breathtaking, interactive graphics on personal computers, game consoles, and mobile devices such as smartphones. The Challenge To keep up with consumer demand for such high-performance gadgets, NVIDIA must meet stringent time-to-market windows. The company's average design cycle is less than six months, from silicon tapeout to printed circuit boards (PCBs) ready for the marketplace. NVIDIA design teams were using Cadence tools to create their IC package and board designs. They had also developed several in-house tools for ball grid array (BGA) fanout and routing to augment their existing Cadence ® Allegro ® constraint-driven PCB design flow. But the pressures of product miniaturization and high-density interconnect (HDI), combined with an increasing number of constraints, was creating new challenges. "NVIDIA designs require a robust, constraint-driven PCB design flow," explains Greg Bodi, NVIDIA Senior Manager, System Design. "Having HDI capabilities driven by that flow is critical for us to meet our time-to-market objectives." The question was whether to invest time and resources developing tools to enable HDI, or to adopt a new solution. And since NVIDIA was designing with high-speed constraints but also using "build-up" technology to handle BGA fanout, they would need a highly flexible solution that could address both sets of requirements. NVIDIA and Cadence "Having tools with the flexibility to drive the high-speed constraints in our designs is paramount to meeting our time to market. Cadence tools give us that flexibility, especially with the HDI functionality….We are shaving up to 25% off our PCB layout design cycle time." Greg Bodi, Senior Manager, System Design, NVIDIA Business Challenges • Tight six-month time-to-market windows • Product miniaturization requires more in-house design tools and skills to optimize high-density interconnect (HDI ) Design Challenges • Handle HDI combined with an increasing number of constraints • Drive micro vias quickly and accurately • Reduce the number of layers on customers' boards • Shorten the overall PCB layout design cycle Cadence Solution • HDI-enabled, constraint-driven PCB design flow • Allegro PCB Design technologies Results • High-speed, constraint-driven HDI flow shortened the PCB design cycle by 25% • Unified PCB design, layout, editing, and routing technologies mitigated risk, boosted performance, and increased efficiency • Collaboration with NVIDIA engineers streamlined time to productivity with the enhanced flow

Articles in this issue

view archives of Cadence PCB success stories - NVIDIA and Cadence