Cadence PCB success stories

www.cadence.com 2 With their combination of Allegro and Sigrity technologies, Imagine Communications can complete more complex designs with higher quality, fewer iterations, and in less time. For example, a large design that previously would have required up to four revisions before going into production now needs only one or two revisions. The teams can assess a board comprehensively, rather than having to evaluate critical components manually as they previously did. "I don't have to worry that I missed something," noted Nevelev. Allegro PCB Designer provides a constraint-driven design flow for concurrent team design, with features including design partitioning, interconnect design planning, and interactive floorplanning and component placement. Allegro EDM Solution provides a collaborative library and design data management environment, while Allegro Design Entry Capture provides the teams with a schematic design tool. The Allegro Sigrity Power- Aware SI Option analyzes source-synchronous parallel buses. With the Sigrity portfolio, the teams have an array of signal integrity analysis as well as board simulation capabilities. "It's just a pleasure to route and design these boards. We actually broke our previous tool, component-wise and net-wise. Doing these really tight, difficult boards with the Allegro tools is great," said Nevelev, adding, "The Sigrity PowerSI ® tool provides an extremely easy and efficient way to extract PCB information into a simulation file. There are quite a few powerful simulation tools on the market, but the PCB extraction portion in the Sigrity tools is probably the best." Imagine Communications' hardware design engineers can quickly check for issues such as impedance violations, reference plane crossing, and space/coupling violations; optimize via structures; and validate compliance with protocol standards such as Ethernet on the whole board using Sigrity technology. For example, running compliance reports on 10G Ethernet traces before building a board saved a full iteration. Being able to validate integrity and timing by using Sigrity SystemSI™ technology to simulate DDR4 parallel buses—something that's difficult to test on a real board—gave the team confidence in their design. On a design with a large number of DDR4 interfaces, the teams were able to build the board, do one revision, prototype, perform full validation, and move into production on schedule with a high degree of confidence in the design. "It was remarkable. To be able to consolidate backdrilling depth with ease on a big board like that was a dream. Now when we release a board to manufacturing, our confidence is pretty high," said Nevelev, adding, "One revision was totally unthinkable before." By working more efficiently, the engineers can focus their efforts on design enhancements. Now, the team can complete a full iteration on a board in a day or two. Previously, the teams had no way to maintain the same kind of schedule with the same level of quality. The teams also appreciate being able to reuse setup components and models in the Sigrity tools, which saves time in subsequent iterations. And using the Team Design Option in Allegro PCB Designer, they can assign two layout designers to work simultaneously on the same file, which essentially cuts the turnaround time in half. "The quality of our designs is totally different, so it's not just about reducing iterations," said Nevelev. "With our older approach, we wouldn't be able to cover everything with this depth. There's only so much you can do manually or semi-manually. If if takes too long, you start to limit simulation efforts to only critical sections. Now, we can easily enter constraints in Allegro PCB Designer and run our designs against them for results on the fly." The team also expects this improved "whole design quality" will reduce hard-to- diagnose field quality issues related to high-speed signal integrity. Not only were the designs created with higher confidence and higher performance, but the cost was reduced as well. In previous versions of designs, retimers were used on the high-speed serial interfaces to clean up the signals that move from board to board through connectors. Using the combination of Allegro and Sigrity technologies, high-speed channels are simulated and optimized at the system level to confirm signal quality standards. The tool suite has allowed Imagine Communications to simulate performance with and without retimers before building the board, which saves an iteration of the PCB build to validate the need for retimers. " One revision was totally unthinkable before. " Boris Nevelev " It was remarkable. To be able to do backdrilling with ease on a big board like that was a dream. Now when we release a board to manufacturing, our confidence is pretty high " Boris Nevelev, Senior Hardware Design Engineer, Imagine Communications

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